We are looking for an experienced RTL Design Engineer to define, design, and integrate RTL for a 5G/6G baseband processing subsystem. The subsystem consists of DSP cores, hardware accelerators, DMA engines, and on-chip interconnects, and is delivered as multiple hardened macros.
Core Skills
RTL Design
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Strong Verilog / VHDL for synthesizable, high-throughput datapath and control logic.
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Ability to take a block from microarchitecture spec to clean RTL.
Subsystem Integration
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Integrating DSP cores, accelerators, DMA, memories and AXI/AHB/APB fabrics.
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Address maps, interrupts, reset and clock domains.
Baseband / DSP Background
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Familiarity with the 5G NR PHY chain (FFT/iFFT, channel estimation, MIMO, LDPC/Polar, beamforming).
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Understanding of fixed-point arithmetic and how the algorithm becomes hardware.
PPA Awareness
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Design for area, timing and power.
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Memory partitioning, pipelining, clock gating and multi-power-domain design (UPF).
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Ability to read synthesis and PnR reports and work closely with the backend team on floorplan and timing closure.
Quality Checks
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Lint, CDC/RDC, synthesis and STA constraints (SDC), and LEC.
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Support verification teams with test planning, coverage closure and debug.
Tools and Flow
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Synopsys or Cadence front-end tools.
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Scripting in Python, Tcl or Perl.
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Version control with Git or similar.
Nice to Have
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Experience with licensable IP or customer-facing subsystem delivery (integration guides, customer support).
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Low-power architecture.
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DFT awareness (scan, MBIST).
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Advanced-node (≤7nm) background.
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Hands-on work integrating licensable DSP cores.
Referral
We are always searching for new talents and welcome your recommendations.
Have someone on your mind? Send their CV to us.
For a successful hire for this position, you will receive a 500 USD Gross bonus.